Organic light emitting display device

ABSTRACT

The present disclosure relates to an organic light emitting display device including a display panel on which a plurality of data lines, a plurality of gate lines, a plurality of first power lines, a plurality of second power lines, and a plurality of pixels are disposed. Each of the plurality of pixels includes: a storage capacitor connected between a first node and a second node; a driving transistor including a gate electrode connected to the second node, a drain electrode connected to the power line, and a source electrode connected to the first node; an organic light emitting diode connected to the first node and the second power line; a first switching transistor connected to the second node and the data lines; and a second switching transistor connected to the first node and the first power lines.

TECHNICAL FIELD

The present disclosure relates to an organic light emitting displaydevice, and more particularly, to an organic light emitting displaydevice which is capable of implementing virtual reality (VR).

DESCRIPTION OF THE RELATED ART

As the information society is developed, demands for display deviceswhich display images are increased in various forms. Recently, a displaydevice for implementing virtual reality is being studied to display aspace which is similar to an actual space.

The virtual reality is an environment which allows people to virtuallyexperience experience/environment, which cannot be actually obtained, bystimulating five senses (visual, auditory, olfactory, taste, and tactilesenses) of human using an artificial technology. The virtual reality maybe implemented through various hardware and software modules such as aninput device, an output device, device driving software, or contents.Generally, a virtual reality implementing device may be configured by aninput unit, a processing unit, and an output unit. Among them, theoutput unit may be configured by a display device with an increasedimmersion degree.

In the virtual reality device, a display device which expressesinformation is very important. Specifically, in order to implementimmersion to the virtual reality, an image expression performance suchas a resolution is important as well as a form of the image. Therefore,as one type of a display device for virtual reality, a head mountdisplay (HMD) is frequently used. As for the HMD, a light and thindisplay device may be advantageously used.

Recently, an organic light emitting display device which will be appliedto a display device serving as an output unit of a virtual realitydevice including the HMD has been studied. The organic light emittingdisplay device is a display device using a self-emitting element using athin light emitting layer between electrodes and is advantageouslyimplemented as a light weight and thin thickness device. Therefore,studies for improving and changing a structure, an operation, or afunction of an organic light emitting display device for a virtualreality device to be suitable for a usage characteristic of the virtualreality device have been deeply performed.

SUMMARY

The inventors of the present disclosure have studied to reduce the sizeof the pixel as much as possible in order to implement the virtualreality using the organic light emitting display device. Therefore, theinventors of the present disclosure configure a pixel circuit with aminimum configuration to reduce the size of the pixel, that is,configure each of a plurality of pixels by three transistors and onecapacitor.

Further, the inventors of the present disclosure design adjacent pixelsto share a vertical line, for example, a power line or a data line toreduce the size of the pixel. However, in the structure shared betweenpixels, a current difference between left and right pixels may beregularly generated due to a variation of a manufacturing process of athin film transistor, which may be visually recognized as a smear.

Therefore, an object to be achieved by the present disclosure is toprovide an organic light emitting display device which reduces thenumber of lines extending to a vertical direction on a display panel toimplement an ultra-high definition.

Further, another object to be achieved by the present disclosure is toprovide an organic light emitting display device in which each pixel isindependently supplied with a voltage without sharing the power line orthe data line with another pixel to constantly maintain a potential of adriving voltage.

Still another object to be achieved by the present disclosure is toprovide an organic light emitting display device which simplifies a gatedriver to reduce a size of a bezel.

Furthermore, still another object to be achieved by the presentdisclosure is to provide an organic light emitting display device whichfixes a potential of the driving voltage to simplify a circuit of apower controller.

Technical objects of the present disclosure are not limited to theabove-mentioned technical objects, and other technical objects, whichare not mentioned above, can be clearly understood by those skilled inthe art from the following descriptions.

According to an aspect of the present disclosure, an organic lightemitting display device includes: a display panel on which a pluralityof data lines, a plurality of gate lines, a plurality of first powerlines, a plurality of second power lines, and a plurality of pixels aredisposed, in which each of the plurality of pixels includes: a storagecapacitor connected between a first node and a second node; a drivingtransistor including a gate electrode connected to the second node, adrain electrode connected to the first power line, and a sourceelectrode connected to the first node; an organic light emitting diodeconnected to the first node and the second power line; a first switchingtransistor connected to the second node and the data line; and a secondswitching transistor connected to the first node and the first powerline. Therefore, the number of power lines is reduced to implement anultra-high definition.

According to another aspect of the present disclosure, an organic lightemitting display device includes: a plurality of data lines; a pluralityof power lines extending in the same direction as the plurality of datalines; a plurality of gate lines intersecting the plurality of datalines and the plurality of power lines; and a plurality of pixelsapplied with voltages from the plurality of data lines, the plurality ofpower lines, and the plurality of gate lines, in which each of theplurality of pixels includes: a driving transistor; a first switchingtransistor which applies a data voltage to a gate electrode of thedriving transistor; a second switching transistor which applies a highpotential driving voltage to a source electrode of the drivingtransistor; a storage capacitor which maintains a voltage applied to thegate electrode and the source electrode of the driving transistor; andan organic light emitting diode which is applied with a current flowingthrough the source electrode of the driving transistor to emit light,and the driving transistor and the second switching transistor share thepower lines. Therefore, a smear of the display panel due to the noise ofthe driving voltage applied to the power line may be avoided.

Other detailed matters of the embodiments are included in the detaileddescription and the drawings.

According to the present disclosure, a size of each pixel of the organiclight emitting display device can be reduced and an additional elementdesign area of the pixel may also be ensured so as to implement anultra-high definition by reducing the number of lines disposed on thedisplay device.

Further, according to the present disclosure, the number of linesdisposed on the display panel is reduced so that a failure rate duringthe process in accordance with simplification of the process may bereduced.

Further, according to the present disclosure, the adjacent pixels do notshare the line so that the smear of the display panel due to a noise ofa driving voltage which is applied to the power line may be avoided.

Further, according to the present disclosure, the number of shiftregisters of the gate driver may be reduced. Therefore, an area of thegate driver is reduced to reduce a non-display area of the display paneland also reduce the size of the bezel.

Furthermore, according to the present disclosure, a potential of a highpotential driving voltage is fixed to remove some of components of apower controller for controlling the high potential driving voltage sothat a circuit of the power controller can be simplified and noises ofdifferent driving voltages due to a potential change of the highpotential driving voltage are avoided. Therefore, an image quality ofthe organic light emitting display device may be increased.

The effects according to the present disclosure are not limited to thecontents exemplified above, and more various effects are included in thepresent specification.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features and other advantages of thepresent disclosure will be more clearly understood from the followingdetailed description taken in con-junction with the accompanyingdrawings, in which:

FIG. 1 is a schematic block diagram for explaining an organic lightemitting display device according to an exemplary embodiment of thepresent disclosure;

FIG. 2 is a circuit diagram illustrating a pixel of an organic lightemitting display device according to an exemplary embodiment of thepresent disclosure;

FIG. 3A is a timing chart for explaining a driving of an organic lightemitting display device according to an exemplary embodiment of thepresent disclosure;

FIG. 3B is a timing chart for explaining a driving of an organic lightemitting display device according to another exemplary embodiment of thepresent disclosure; and

FIGS. 4 to 6 are timing charts for explaining a driving of an organiclight emitting display device according to various exemplary embodimentsof the present disclosure.

DETAILED DESCRIPTION

Advantages and characteristics of the present disclosure and a method ofachieving the advantages and characteristics will be clear by referringto exemplary embodiments described below in detail together with theaccompanying drawings. However, the present disclosure is not limited tothe exemplary embodiments disclosed herein but will be implemented invarious forms. The exemplary embodiments are provided by way of exampleonly so that a person of ordinary skilled in the art can fullyunderstand the disclosures of the present disclosure and the scope ofthe present disclosure. Therefore, the present disclosure will bedefined only by the scope of the appended claims.

Further, in the following description, a detailed explanation of knownrelated technologies may be omitted to avoid unnecessarily obscuring thesubject matter of the present disclosure. The terms such as “including,”“having,” and “consist of” used herein are generally intended to allowother components to be added unless the terms are used with the term“only”. Any references to singular may include plural unless expresslystated otherwise.

Components are interpreted to include an ordinary error range even ifnot expressly stated.

Although the terms “first”, “second”, and the like are used fordescribing various components, these components are not confined bythese terms. These terms are merely used for distinguishing onecomponent from the other components. Therefore, a first component to bementioned below may be a second component in a technical concept of thepresent disclosure.

Like reference numerals indicate like elements throughout thespecification.

The features of various embodiments of the present disclosure can bepartially or entirely bonded to or combined with each other and can beinterlocked and operated in technically various ways which areunderstandable by those skilled in the art, and the embodiments can becarried out independently of or in association with each other.

Hereinafter, various exemplary embodiments of the present disclosurewill be described in detail with reference to accompanying drawings.

FIG. 1 is a schematic block diagram of a display device according to anexemplary embodiment of the present disclosure. Referring to FIG. 1, anorganic light emitting display device 100 according to an exemplaryembodiment of the present disclosure includes a display panel 110, adata driver 120, a gate driver 130, a timing controller 140, and a powercontroller 150.

The display panel 110 includes a plurality of gate lines GL and aplurality of data lines DL which intersect each other in a matrix on thesubstrate using glass or plastic. A plurality of pixels Px is defined bythe plurality of gate lines GL and the data lines DL.

The plurality of pixels Px of the display panel 110 is connected to thegate lines GL, the data lines DL, and the power lines PL. The pluralityof pixels Px is applied with a driving voltage from the power lines PLto be driven based on a gate voltage transmitted from the gate lines GLand a data voltage transmitted from the data lines DL.

More specifically, the plurality of pixels applies a current to organiclight emitting diodes OLED disposed on the plurality of pixels Px, basedon the gate voltage and the data voltage. Electrons and holes dischargeddue to the current which is applied to the organic light emitting diodesOLED are coupled to generate excitons. The generated excitons emit lightto implement a gray scale of the organic light emitting display device100.

The plurality of pixels Px may implement light of a specific color. Forexample, the plurality of pixels Px may be configured by a red pixelwhich implements red, a green pixel which implements green, and a bluepixel which implements blue, but is not limited thereto.

The timing controller 140 supplies a data control signal DCS to the datadriver 120 to control the data driver 120 and supplies a gate controlsignal GCS to the gate driver 130 to control the gate driver 130, andsupplies a power control signal PCS to the power controller 150 tocontrol the power controller 150.

The timing controller 140 starts scanning in accordance with a timingimplemented by each frame, based on the timing signal TS received froman external host system. The timing controller 140 converts a videosignal VS received from the external host system in accordance with adata signal format which is processible in the data driver 120 to outputvideo data RGB. By doing this, the timing controller 140 controls datadriving at an appropriate timing in accordance with the scanning.

The timing controller 140 receives various timing signals TS including avertical synchronization signal Vsync, a vertical synchronization signalHsync, a data enable signal DE, a data clock signal DCLK together withthe video signal VS from the external host system.

In order to control the data driver 120, the gate driver 130, and thepower controller 150, the timing controller 140 receives the timingsignal TS such as the vertical synchronization signal Vsync, thehorizontal synchronization signal Hsync, the data enable signal DE, andthe data clock signal DCLK and generates various control signals DCS,GCS, and PCS. The timing controller 140 outputs the various controlsignals DCS, GCS, and PCS to the data driver 120, the gate driver 130,and the power controller 150.

For example, in order to control the gate driver 130, the timingcontroller 140 outputs various gate control signals GCS including a gatestart pulse GSP, a gate shift clock GSC, and a gate output enable signalGOE.

Here, the gate start pulse controls an operation start timing of one ormore gate circuits which configure the gate driver 130. The gate shiftclock is a clock signal which is commonly input to one or more gatecircuits and controls a shift timing of the scan signal (gate pulse).The gate output enable signal designates timing information of one ormore gate circuits.

Further, in order to control the data driver 120, the timing controller140 outputs various data control signals DCS including a source startpulse SSP, a source sampling clock SSC, and a source output enablesignal SOE.

Here, the source start pulse controls a data sampling start timing ofone or more data circuits which configure the data driver 120. Thesource sampling clock is a clock signal which controls a sampling timingof data in each data circuit. The source output enable signal controlsan output timing of the data driver 120.

The timing controller 140 may be disposed on a control printed circuitboard connected to a source printed circuit board to which the datadriver 120 is bonded, through a connecting medium such as a flexibleflat cable FFC or a flexible printed circuit FPC.

The gate driver 130 sequentially supplies a high potential (on-level) ora low potential (off-level) gate voltage to the gate lines GL inaccordance with the control of the timing controller 140. Here, the gatelines GL may be divided into a first gate line GL1 through which a firstgate voltage GS1 is applied and a second gate line GL2 through which thesecond gate voltage GS2 is applied.

According to a driving method, the gate driver 130 may be located onlyat one side of the display panel 110 or located at both sides ifnecessary.

The gate driver 130 may be connected to a bonding pad of the displaypanel 110 by a tape automated bonding (TAB) method or a chip on glass(COG) method. The gate driver 130 may also be implemented in a gate inpanel (GIP) type to be directly disposed on the display panel 110 or maybe disposed to be integrated with the display panel 110, if necessary.

The gate driver 130 may include a shift register or a level shifter.

The data driver 120 converts video data RGB received from the timingcontroller 140 into an analog data voltage Vdata and output the analogdata voltage to the data lines DL.

The data driver 120 is connected to the bonding pad of the display panel110 by a tape automated bonding method or a chip on glass method or maybe directly disposed on the display panel 110. If necessary, the datadriver 120 may be disposed to be integrated with the display panel 110.

Further, the data driver 120 may be implemented by a chip on film (COF)method. In this case, one end of the data driver 120 may be bonded to atleast one source printed circuit board and the other end may be bondedto the display panel 110.

The data driver 120 may include a logic unit including various circuitssuch as a level shifter or a latch unit, a digital analog converter DAC,and an output buffer.

The power controller 150 may supply various voltages or currents to thedisplay panel 110, the data driver 120, and the gate driver 130 orcontrol various voltages or currents to be supplied. The powercontroller may also be referred to as a power management integratedcircuit (PMIC).

The power controller 150 may apply a high potential driving voltage Vddand a low potential driving voltage Vss to each of the plurality ofpixels Px through the power lines PL.

Specifically, the power driver 150 may apply the high potential drivingvoltage Vdd to each of the plurality of pixels Px through the firstpower line PL1 and apply the low potential driving voltage Vss throughthe second power line PL2.

Here, the high potential driving voltage Vdd and the low potentialdriving voltage Vss may not be a fixed potential value, but may be avariable potential voltage.

The source printed circuit board and the control printed circuit boarddescribed above may be configured by one printed circuit board.

Additionally, the organic light emitting display device 100 according tothe exemplary embodiment of the present disclosure may further includevarious additional elements for generating various signals or drivingthe pixels of the display panel. The additional elements for driving thepixels may include an inverter circuit, a multiplexer, or anelectrostatic discharging circuit. The organic light emitting displaydevice 100 may also include an additional element associated with afunction other than a pixel driving function. For example, the organiclight emitting display device 100 may include additional elements whichprovide a touch sensing function, a user authentication function (forexample, fingerprint recognition), a multilevel pressure sensingfunction, or a tactile feedback function.

Hereinafter, a circuit structure of a pixel of an organic light emittingdisplay device 100 according to an exemplary embodiment of the presentdisclosure will be described in detail with reference to FIG. 2.

FIG. 2 is a circuit diagram illustrating a pixel of an organic lightemitting display device according to an exemplary embodiment of thepresent disclosure.

Referring to FIG. 2, each of the plurality of pixels Px includes anorganic light emitting diode OLED which emits light, a drivingtransistor Td which drives the organic light emitting diode OLED, afirst switching transistor Ts1 and a second switching transistor Ts2which control the driving transistor Td, and a storage capacitor Cstwhich maintains a voltage between a gate electrode g and a sourceelectrode s of the driving transistor Td for one frame.

The driving transistor Td controls the gray scale of the organic lightemitting display device 100 in accordance with the data voltage Vdata byadjusting an amount of current flowing in the organic light emittingdiode OLED.

Specifically, the gate electrode g of the driving transistor Td isconnected to a second node N2, the drain electrode d of the drivingtransistor Td is connected to the first power line PL1, and the sourceelectrode s of the driving transistor Td is connected to the first nodeN1. Here, a variable high potential driving voltage Vdd may be appliedto the first power line PL1.

Although the source electrode s and the drain electrode d of the drivingtransistor Td are set on the basis of an n-type transistor, theelectrodes of the driving transistor Td may also be set on the basis ofa p-type transistor.

When the data voltage Vdata is applied to the second node N2 through thefirst switching transistor Ts1, a value of current Ids flowing betweenthe drain electrode d and the source electrode s of the drivingtransistor Td is determined depending on a voltage Vgs between the gateelectrode g and the source electrode s of the driving transistor Td.

The organic light emitting diode OLED is applied with the current Idsfrom the driving transistor Td to emit light to implement a gray scalecorresponding to the current Ids value.

Specifically, the organic light emitting diode OLED includes a firstelectrode and a second electrode. Here, the first electrode may be ananode and the second electrode may be a cathode. An organic lightemitting layer may be disposed between the first electrode and thesecond electrode. The first electrode of the organic light emittingdiode OLED is connected to the first node N1 and the second electrode isconnected to the second power line PL2. Here, a variable low potentialdriving voltage Vss may be applied to the second power line PL2.

The storage capacitor Cst is connected between the first node N1 and thesecond node N2 to maintain the voltage Vgs between the gate electrode gand the source electrode s of the driving transistor Td during apredetermined period.

The first switching transistor Ts1 is switched by a first gate voltageGS1 applied through the first gate line GL1. That is, the firstswitching transistor Ts1 is turned on by the first gate voltage GS1 toapply the data voltage Vdata to the second node N2.

Specifically, the gate electrode g of the first switching transistor Ts1is connected to the first gate line GL1, the drain electrode d of thefirst switching transistor Ts1 is connected to the data line DL, and thesource electrode s of the first switching transistor Ts1 is connected tothe second node N2.

The second switching transistor Ts2 is switched by a second gate voltageGS2 applied through the second gate line GL2. That is, the secondswitching transistor Ts2 is turned on by the second gate voltage GS2 toapply the high potential driving voltage Vdd to the first node N1.

Specifically, the gate electrode g of the second switching transistorTs2 is connected to the second gate line GL2, the drain electrode d ofthe second switching transistor Ts2 is connected to the first power linePL1, and the source electrode s of the second switching transistor Ts2is connected to the first node N1.

FIG. 3A is a timing chart for explaining a driving of an organic lightemitting display device according to an exemplary embodiment of thepresent disclosure.

Referring to FIG. 3A, one frame is divided into a first period P1 and asecond period P2. The first period P1 is a data write and hold periodwhen the data voltage Vdata is written in each pixel Px and ismaintained for a predetermined time and the second period P2 includes anemission period when light is emitted in accordance with the writtendata. That is, during the second period P2, the organic light emittingdiode OLED may emit light.

As illustrated in FIG. 3A, during the first period P1, the first gatevoltage GS1 and the second gate voltage GS2 which are high potentialsare sequentially applied to the first gate line GL1 and the second gateline GL2 which are connected to the plurality of pixels Px of each rowdisposed on the display panel 110 only during one horizontal period(1H). Therefore, the first switching transistor Ts1 and the secondswitching transistor Ts2 disposed in the plurality of pixels Px of eachrow are turned on only during one horizontal period (1H).

Specifically, the first gate voltage GS1_1 _(st) and the second gatevoltage GS2_1 _(st) which are high potentials are applied to a firstfirst gate line GL1 and a first second gate line GL2 during onehorizontal period (1H) in accordance with a rising timing of thevertical synchronization signal Vsync. Therefore, the first switchingtransistor Ts1 and the second switching transistor Ts2 disposed in theplurality of pixels Px of the first row are turned on. Thereafter, afirst gate voltage GS1_1 _(st) and a second gate voltage GS2_1st whichare low potentials are applied to a first first gate line GL1 and afirst second gate line GL2 during one horizontal period (1H) so that thefirst switching transistor Ts1 and the second switching transistor Ts2disposed in the plurality of pixels Px of the first row are turned off.Simultaneously, a first gate voltage GS1_2nd and a second gate voltageGS2_2nd which are high potentials are applied to a second first gateline GL1 and a second second gate line GL2 during one horizontal period(1H) so that the first switching transistor Ts1 and the second switchingtransistor Ts2 disposed in a plurality of pixels Px of a second row areturned on. By repeating this operation, finally, a first gate voltageGS1 last and a second gate voltage GS2 last which are high potentialsare applied to a last first gate line GL1 and a last second gate lineGL2 during one horizontal period (1H) so that the first switchingtransistor Ts1 and the second switching transistor Ts2 disposed in aplurality of pixels Px of a last row are turned on.

Here, the high potential first gate voltage GS1 and the high potentialsecond gate voltage GS2 may be the same potential. For example, highpotential voltages of the high potential first gate voltage GS1 and thehigh potential second gate voltage GS2 may be set to be 8 V or higher.The first gate voltage GS1 and the second gate voltage GS2 are set asdescribed above to turn on the first switching transistor Ts1 and thesecond switching transistor Ts2.

During the first period P1, a high potential driving voltage Vdd whichis applied to the first power line PL1 may be set to be a firstpotential V1 and a low potential driving voltage Vss which is applied tothe second power line PL2 may be set to be a third potential V3. Here,the third potential V3 may have a value between the first potential V1and a fourth potential V4 which will be described below. For example,the first potential V1 may be 1 V, the third potential V3 may be 0 V to1 V, and the fourth potential V4 may be 0 V. The relationship of thethird potential V3 is set as described above so that the organic lightemitting diode OLED may be suppressed from emitting light during thefirst period P1 which is a data write and hold period.

As described above, during the first period P1, the first gate voltageGS1, the second gate voltage GS2, the high potential driving voltageVdd, and the low potential driving voltage Vss are applied. By doingthis, the second node N2 connected to the source electrode s of thefirst switching transistor Ts1 is applied with the data voltage Vdataand the first node N1 connected to the source electrode s of the secondswitching transistor Ts2 is applied with a high potential drivingvoltage Vdd which is the first potential V1.

Accordingly, since the source electrode s and the drain electrode d ofthe driving transistor Td are applied with the same voltage which is thehigh potential driving voltage Vdd of the first potential V1, thecurrent Ids does not flow in the source electrode s and the drainelectrode d of the driving transistor Td. Therefore, the organic lightemitting diode OLED does not emit light.

However, a potential difference Vgs of the gate electrode g and thesource electrode s of the driving transistor Td which is a potentialdifference of the second node N2 and the first node N1 is maintained sothat the data is written in the driving transistor Td of each pixel Px.

Next, the organic light emitting diode OLED emits light by the datawritten in each pixel during the second period P2.

During the second period P2, the low potential first gate voltage GS1and the low potential second gate voltage GS2 are applied to both thefirst gate line GL1 and the second gate line GL2. Accordingly, the firstswitching transistor Ts1 and the second switching transistor Ts2 aremaintained to be turned off.

However, during the second period P2, the high potential driving voltageVdd which is applied to the first power line PL1 may be set to be asecond potential V2 and a low potential driving voltage Vss which isapplied to the second power line PL2 may be set to be a fourth potentialV4. Here, the second potential V2 is higher than the first potential V1and the fourth potential V4 is lower than the third potential V3. Apotential difference between the second potential V2 and the fourthpotential V4 may be 8.5 V to 10 V. For example, the second potential V2may be 8.5 V to 10 V and the fourth potential V4 may be 0 V.

As described above, a voltage applied to the drain electrode d of thedriving transistor Td rises by setting the high potential drivingvoltage Vdd to be 8.5 V to 10 V to flow the current Ids between thedrain electrode d and the source electrode s of the driving transistorTd. Since the amount of flowing current Ids is determined based on thevoltage Vgs of the gate electrode g and the source electrode s of thedriving transistor Td, the amount of flowing current Ids is determinedbased on the data voltage Vdata. Therefore, the organic light emittingdiode OLED applied with the driving current Ids emits light to express agray scale corresponding to the data voltage Vdata.

As described above, both the first switching transistor Ts1 and thedriving transistor Td of the organic light emitting display device 100according to the exemplary embodiment of the present disclosure areconnected to the first power line PL1 and raise the high potentialdriving voltage Vdd which is applied to the first power line PL1 fromthe first potential V1 to the second potential V2 during the secondperiod P2 which is an emission period.

Therefore, the driving transistor Td may be applied with the highpotential driving voltage Vdd having a second potential V2 which is thehigh potential driving voltage Vdd of the related art through the firstpower line PL1 during the second period P2. The second switchingtransistor Ts2 may be applied with the high potential driving voltageVdd having a first potential V1 which is the reference voltage of therelated art through the first power line PL1 during the first period P1.By doing this, the pixel Px of the organic light emitting display deviceaccording to the exemplary embodiment of the present disclosure maycombine the reference voltage line and the high potential drivingvoltage line of the related art to the first power line PL1.

Therefore, the organic light emitting display device according to theexemplary embodiment of the present disclosure may not only reduce thesize of each pixel Px of the organic light emitting display device butalso ensure an additional element design area of the pixel Px, so as toimplement an ultra-high definition. Further, the number of linesdisposed on the display panel 110 is reduced so that a failure rateduring the process in accordance with simplification of the process maybe reduced.

FIG. 3B is a timing chart for explaining a driving of an organic lightemitting display device according to another exemplary embodiment of thepresent disclosure.

Hereinafter, the driving of an organic light emitting display deviceaccording to another exemplary embodiment of the present disclosure willbe described with reference to FIG. 3B. Since a circuit structure of apixel disposed in the organic light emitting display device according toanother exemplary embodiment of the present disclosure is the same asthe pixel circuit structure of the organic light emitting display deviceaccording to the exemplary embodiment of the present disclosure, adescription of the circuit structure of the pixel will be omitted.Further, only the difference between the driving of the organic lightemitting display device according to another exemplary embodiment of thepresent disclosure and the driving of the organic light emitting displaydevice according to the exemplary embodiment of the present disclosureis a method of applying a low potential driving voltage. Therefore, themethod of applying a low potential driving voltage will be mainlydescribed.

During the first period P1, a high potential driving voltage Vdd whichis applied to the first power line PL1 may be set to be a firstpotential V1 and a low potential driving voltage Vss which is applied tothe second power line PL2 may be set to be a fourth potential V4.

Further, during the second period P2, the high potential driving voltageVdd which is applied to the first power line PL1 may be set to be asecond potential V2 and a low potential driving voltage Vss which isapplied to the second power line PL2 may be set to be a fourth potentialV4. That is, the low potential driving voltage Vss during the firstperiod P1 and the second period P2 is maintained to be the fourthpotential V4.

For example, the first potential V1 may be 1 V, the second potential V2may be 8.5 V to 10 V, and the fourth potential V4 may be 0 V.

As described above, since the potential of the low potential drivingpotential Vss is constantly maintained, noises of different drivingvoltages due to the potential change of the high potential drivingvoltage Vdd are avoided so that an image quality of the organic lightemitting display device 100 may be improved.

FIGS. 4 to 6 are timing charts for explaining a driving of an organiclight emitting display device according to various exemplary embodimentsof the present disclosure.

Hereinafter, the driving of an organic light emitting display deviceaccording to still another exemplary embodiment of the presentdisclosure will be described with reference to FIG. 4. Since a circuitstructure of a pixel disposed in the organic light emitting displaydevice according to another exemplary embodiment of the presentdisclosure is the same as the pixel circuit structure of the organiclight emitting display device according to the exemplary embodiment ofthe present disclosure, a description of the circuit structure of thepixel will be omitted. Further, only the difference between the drivingof the organic light emitting display device according to anotherexemplary embodiment of the present disclosure and the driving of theorganic light emitting display device according to the exemplaryembodiment of the present disclosure is a method of applying a secondgate voltage. Therefore, the method of applying a second gate voltagewill be mainly described.

As illustrated in FIG. 4, during the first period P1, the first gatevoltage GS1 which is a high potential is sequentially applied to thefirst gate lines GL1 which are connected to the plurality of pixels Pxof each row disposed on the display panel 110 only during one horizontalperiod (1H) and the high potential second gate voltage GS2 is appliedduring the first period P1. Therefore, the first switching transistorTs1 disposed in the plurality of pixels Px of each row is turned on onlyduring one horizontal period (1H) but the second switching transistorTs2 disposed in the plurality of pixels Px of each row is continuouslyturned on during the first period P1.

Specifically, the first gate voltage GS1_1st which is a high potentialis applied to the first first gate line GL1 during one horizontal period(1H) in accordance with a rising timing of the vertical synchronizationsignal Vsync to turn on the first switching transistor Ts1 disposed inthe plurality of pixels Px of the first row. Thereafter, the first gatevoltage GS1_1st which is a low potential is applied to the first firstgate line GL1 to turn off the first switching transistor Ts1 disposed inthe plurality of pixels Px of the first row. Simultaneously, a firstgate voltage GS_2nd which is a high potential is applied to the secondfirst gate line GL1 during one horizontal period (1H) to turn on thefirst switching transistor Ts1 disposed in the plurality of pixels Px ofthe second row. By repeating the above operation, a first gate voltageGS1 last which is a high potential is applied to the last first gateline GL1 during one horizontal period (1H) to turn on the firstswitching transistor Ts1 disposed in the plurality of pixels Px of thelast row.

In contrast, during the first period P1, a second gate voltage of a highpotential (GS2 common) is applied to the second gate lines GL2 of allrows so that the first switching transistor Ts1 is continuously turnedon.

Here, the high potential first gate voltage GS1 and the high potentialsecond gate voltage GS2 may be the same potential. For example, highpotential voltages of the high potential first gate voltage GS1 and thehigh potential second gate voltage GS2 may be set to be 8 V or higher.The first gate voltage GS1 and the second gate voltage GS2 are set asdescribed above to turn on the first switching transistor Ts1 and thesecond switching transistor Ts2.

As described above, during the first period P1, the first gate voltageGS1, the second gate voltage GS2, the high potential driving voltageVdd, and the low potential driving voltage Vss are applied. By doingthis, the second node N2 connected to the source electrode s of thefirst switching transistor Ts1 is applied with the data voltage Vdataand the first node N1 connected to the source electrode s of the secondswitching transistor Ts2 is applied with a high potential drivingvoltage Vdd which is the first potential V1.

Accordingly, since the source electrode s and the drain electrode d ofthe driving transistor Td are applied with the same voltage which is thehigh potential driving voltage Vdd of the first potential V1, thecurrent Ids does not flow in the source electrode s and the drainelectrode d of the driving transistor Td. Therefore, the organic lightemitting diode OLED does not emit light.

However, a potential difference Vgs of the gate electrode g and thesource electrode s of the driving transistor Td which is the potentialdifference of the second node N2 and the first node N1 is maintained sothat the data is written in the driving transistor Td of each pixel Px.

Next, the organic light emitting diode OLED emits light by the datawritten in each pixel during the second period P2.

During the second period P2, the low potential first gate voltage GS1and the low potential second gate voltage GS2 are applied to both thefirst gate line GL1 and the second gate line GL2. Accordingly, the firstswitching transistor Ts1 and the second switching transistor Ts2 aremaintained to be turned off.

Further, a voltage applied to the drain electrode d of the drivingtransistor Td rises to flow the current Ids between the drain electroded and the source electrode s of the driving transistor Td. Since theamount of flowing current Ids is determined based on the voltage Vgs ofthe gate electrode g and the source electrode s of the drivingtransistor Td, the amount of flowing current Ids is determined based onthe data voltage Vdata. Therefore, the organic light emitting diode OLEDapplied with the driving current Ids emits light to express a gray scalecorresponding to the data voltage Vdata.

As described above, in the organic light emitting display deviceaccording to another exemplary embodiment of the present disclosure, thefirst gate voltage GS1 is sequentially shifted by one horizontal period(1H) during the first period P1, but the second gate voltage GS2 iscontinuously maintained to be a high potential during the first period.

Therefore, there is no need to sequentially shift the second gatevoltage GS2 by one horizontal period (1H) similarly to the first gatevoltage GS1, so that the number of shift registers of the gate driver130 may be reduced. Accordingly, the area of the gate driver 130 isreduced so that the area of the control printed circuit board is reducedand the non-display area of the display panel 110 is reduced so that abezel size is also reduced.

Further, similarly to the other exemplary embodiment, also in anotherexemplary embodiment of the present disclosure, during the first periodP1, a high potential driving voltage Vdd which is applied to the firstpower line PL1 may be set to be a first potential V1 and a low potentialdriving voltage Vss which is applied to the second power line PL2 may beset to be a fourth potential V4. Further, during the second period P2,the high potential driving voltage Vdd which is applied to the firstpower line PL1 may be set to be a second potential V2 and a lowpotential driving voltage Vss which is applied to the second power linePL2 may be set to be a fourth potential V4. That is, the low potentialdriving voltage Vss during the first period P1 and the second period P2is maintained to be the fourth potential V4.

For example, the first potential V1 may be 1 V, the second potential V2may be 8.5 V to 10 V, and the fourth potential V4 may be 0 V.

As described above, since the potential of the low potential drivingvoltage Vss is constantly maintained, noises of different drivingvoltages due to the potential change of the high potential drivingvoltage Vdd are avoided so that an image quality of the organic lightemitting display device 100 may be improved.

Hereinafter, the driving of an organic light emitting display deviceaccording to still another exemplary embodiment of the presentdisclosure will be described with reference to FIGS. 5 and 6. Since acircuit structure of a pixel disposed in the organic light emittingdisplay device according to another exemplary embodiment of the presentdisclosure is the same as the pixel circuit structure of the organiclight emitting display device according to the exemplary embodiment ofthe present disclosure, a description of the circuit structure of thepixel will be omitted. Further, only the difference between the drivingof the organic light emitting display device according to anotherexemplary embodiment of the present disclosure and the driving of theorganic light emitting display device according to the exemplaryembodiment of the present disclosure is a high potential second gatevoltage. Therefore, the high potential second gate voltage will bemainly described.

Referring to FIGS. 5 and 6, in the organic light emitting display deviceaccording to another exemplary embodiment of the present disclosure, ahigh potential second gate voltage Vg2 is lower than a high potentialfirst gate voltage Vg1. Specifically, the high potential second gatevoltage Vg2 may be a sum of the high potential driving voltage Vddhaving a first potential V1 and a threshold voltage Vth of the secondswitching transistor Ts2. For example, when the threshold voltage Vth ofthe second switching transistor Ts2 is 1 V and the high potentialdriving voltage Vdd having the first potential V1 is also 1 V, the highpotential second gate voltage Vg2 may be 2 V.

Further, a high potential driving voltage Vdd which is applied to thefirst power line PL1 during the first period P1 may be set to be asecond potential V2 and a low potential driving voltage Vss which isapplied to the second power line PL2 may be set to be a third potentialV3.

As described above, during the first period P1, the high potential firstgate voltage Vg1, the high potential second gate voltage Vg2, the highpotential driving voltage Vdd, and the low potential driving voltage Vssare applied. By doing this, the second node N2 connected to the sourceelectrode s of the first switching transistor Ts1 is applied with thedata voltage Vdata and the first node N1 connected to the sourceelectrode s of the second switching transistor Ts2 is applied with adriving voltage Vdd having a first potential V1 which is a differencebetween the high potential second gate voltage Vg2 and the thresholdvoltage Vth of the second switching transistor Ts2. That is, the firstnode N1 is applied with 1 V which is a driving voltage Vdd having afirst potential V1 corresponding to the difference between 2 V of thehigh potential second gate voltage Vg2 and 1 V of the threshold voltageVth of the second switching transistor Ts2.

Further, during the second period P2, the low potential first gatevoltage GS1 and the low potential second gate voltage GS2 are applied toboth the first gate line GL1 and the second gate line GL2. Accordingly,the first switching transistor Ts1 and the second switching transistorTs2 are maintained to be turned off.

Further, during the second period P2, the high potential driving voltageVdd which is applied to the first power line PL1 may be maintained to bea second potential V2 similarly to the first period P1 and a lowpotential driving voltage Vss which is applied to the second power linePL2 may be set to be a fourth potential V4.

As described above, the low potential driving voltage Vss having thefourth potential V4 is set to flow the current Ids between the drainelectrode d and the source electrode s of the driving transistor Td.Since the amount of flowing current Ids is determined based on thevoltage Vgs of the gate electrode g and the source electrode s of thedriving transistor Td, the amount of flowing current Ids is determinedbased on the data voltage Vdata. Therefore, the organic light emittingdiode OLED applied with the driving current Ids emits light to express agray scale corresponding to the data voltage Vdata.

As described above, in another organic light emitting display device ofthe present disclosure, the high potential second gate voltage Vg2 maybe set to be a sum of the high potential driving voltage Vdd having afirst potential V1 and a threshold voltage Vth of the second switchingtransistor Ts2. That is, the high potential second gate voltage Vg2 maybe set to be lower than a sum of the high potential driving voltage Vddhaving a second potential V2 which is applied during the first periodand a threshold voltage Vth of the second switching transistor Ts2. Thehigh potential second gate voltage Vg2 is set as described above so thatduring the first period P1 and the second period P2, the high potentialdriving voltage Vdd applied to the first power line PL1 may becontinuously fixed to be a second potential V2.

Therefore, the organic light emitting display device 100 may be drivenonly by controlling the low potential driving voltage Vss whileconstantly maintaining the potential of the high potential drivingvoltage Vdd.

Accordingly, the potential of the high potential driving voltage Vdd isconstantly maintained so that some components of the power controller150 for controlling the high potential driving voltage Vdd may beremoved, to achieve circuit simplification of the power controller 150.

Further, since the potential of the high potential driving voltage Vddis constantly maintained, noises of different driving voltages due tothe potential change of the high potential driving voltage Vdd areavoided so that an image quality of the organic light emitting displaydevice 100 may be improved.

The exemplary embodiments of the present disclosure can also bedescribed as follows:

According to an aspect of the present disclosure, an organic lightemitting display device includes: a display panel on which a pluralityof data lines, a plurality of gate lines, a plurality of first powerlines, a plurality of second power lines, and a plurality of pixels aredisposed, in which each of the plurality of pixels includes: a storagecapacitor connected between a first node and a second node; a drivingtransistor including a gate electrode connected to the second node, adrain electrode connected to the first power line, and a sourceelectrode connected to the first node; an organic light emitting diodeconnected to the first node and the second power line; a first switchingtransistor connected to the second node and the data line; and a secondswitching transistor connected to the first node and the first powerline.

According to another aspect of the present disclosure, the organic lightemitting display device may be driven by separating a first period whena data voltage is applied to the gate electrode of the drivingtransistor and a second period when the organic light emitting diodeemits light based on the data voltage.

According to still another aspect of the present disclosure, a highpotential driving voltage having a first potential is applied to theplurality of first power lines during the first period, a high potentialdriving voltage having a second potential is applied to the plurality offirst power lines during the second period, and the second potential ishigher than the first potential.

According to still another aspect of the present disclosure, a lowpotential driving voltage having a third potential is applied to theplurality of second power lines during the first period, a low potentialdriving voltage having a fourth potential is applied to the plurality ofsecond power lines during the second period, and the third potential ishigher than the fourth potential.

According to still another aspect of the present disclosure, during thefirst period and the second period, a low potential driving voltagehaving a third potential is applied to the plurality of second powerlines.

According to still another aspect of the present disclosure, a highpotential driving voltage having a first potential is applied to theplurality of first power lines during the first period and the secondperiod, a low potential driving voltage having a third potential isapplied to the plurality of second power lines during the first period,a low potential driving voltage having a fourth potential is applied tothe plurality of second power lines during the second period, and thethird potential is higher than the fourth potential.

According to still another aspect of the present disclosure, the thirdpotential is lower than the first potential.

According to still another aspect of the present disclosure, theplurality of gate lines includes a plurality of first gate lines and aplurality of second gate lines, the first switching transistor isswitched through a first gate voltage applied through the plurality offirst gate lines, and the second switching transistor is switchedthrough a second gate voltage applied through the plurality of secondgate lines.

According to still another aspect of the present disclosure, the firstgate voltage and the second gate voltage are high potentials only duringone horizontal period of the first period.

According to still another aspect of the present disclosure, the firstgate voltage is a high potential only during one horizontal period ofthe first period and the second gate voltage is a high potential duringthe entire first period.

According to still another aspect of the present disclosure, the highpotential of the second gate voltage is lower than the high potential ofthe first gate voltage.

According to still another aspect of the present disclosure, the highpotential of the second gate voltage is lower than a sum of the highpotential driving voltage applied during the first period and athreshold voltage of the second switching transistor.

According to another aspect of the present disclosure, an organic lightemitting display device includes: a plurality of data lines; a pluralityof power lines extending in the same direction as the plurality of datalines; a plurality of gate lines intersecting the plurality of datalines and the plurality of power lines; and a plurality of pixelsapplied with voltages from the plurality of data lines, the plurality ofpower lines, and the plurality of gate lines, in which each of theplurality of pixels includes: a driving transistor; a first switchingtransistor which applies a data voltage to a gate electrode of thedriving transistor; a second switching transistor which applies a highpotential driving voltage to a source electrode of the drivingtransistor; a storage capacitor which maintains a voltage applied to thegate electrode and the source electrode of the driving transistor; andan organic light emitting diode which is applied with a current flowingthrough the source electrode of the driving transistor to emit light,and the driving transistor and the second switching transistor share thepower lines.

According to another aspect of the present disclosure, a potential of avoltage applied to the power lines rises during a period when theorganic light emitting diode emits light.

According to still another aspect of the present disclosure, theplurality of gate lines includes a plurality of first gate linesconnected to the first switching transistors and a plurality of secondgate lines connected to the second switching transistors and a highpotential of the second gate voltage which is applied to the pluralityof second gate lines is lower than a high potential of the first gatevoltage which is applied to the first gate lines.

Although the exemplary embodiments of the present disclosure have beendescribed in detail with reference to the accompanying drawings, thepresent disclosure is not limited thereto and may be embodied in manydifferent forms without departing from the technical concept of thepresent disclosure. Accordingly, the exemplary embodiments disclosedherein are not intended to limit but describe the technical spirit ofthe present disclosure and the scope of the technical spirit of thepresent disclosure is not restricted by the exemplary embodiments.Therefore, it should be understood that the above-described exemplaryembodiments are illustrative in all aspects and do not limit the presentdisclosure. The protective scope of the present disclosure should beconstrued based on the following claims, and all the technical conceptsin the equivalent scope thereof should be construed as falling withinthe scope of the present disclosure.

The invention claimed is:
 1. An organic light emitting display device,comprising: a display panel on which a plurality of data lines, aplurality of gate lines, a plurality of first power lines, a pluralityof second power lines, and a plurality of pixels are disposed, whereineach of the plurality of pixels includes: a storage capacitor connectedbetween a first node and a second node; a driving transistor including agate electrode connected to the second node, a drain electrode connectedto one of the plurality of first power lines, and a source electrodeconnected to the first node; an organic light emitting diode connectedto the first node and one of the plurality of second power lines; afirst switching transistor connected to the second node and one of theplurality of data lines; and a second switching transistor connected tothe first node and the one of the plurality of first power lines,wherein the plurality of gate lines includes a plurality of first gatelines and a plurality of second gate lines, the first switchingtransistor is switched through a first gate voltage applied through oneof the plurality of first gate lines, and the second switchingtransistor is switched through a second gate voltage applied through oneof the plurality of second gate lines, wherein a high potential of thesecond gate voltage is less than a high potential of the first gatevoltage.
 2. The organic light emitting display device according to claim1, wherein the organic light emitting display device is driven byseparating a first period when a data voltage is applied to the gateelectrode of the driving transistor and a second period when the organiclight emitting diode emits light based on the data voltage.
 3. Theorganic light emitting display device according to claim 2, wherein ahigh potential driving voltage having a first potential is applied tothe plurality of first power lines during the first period, a highpotential driving voltage having a second potential is applied to theplurality of first power lines during the second period, wherein thesecond potential is higher than the first potential.
 4. The organiclight emitting display device according to claim 3, wherein a lowpotential driving voltage having a third potential is applied to theplurality of second power lines during the first period, a low potentialdriving voltage having a fourth potential is applied to the plurality ofsecond power lines during the second period, wherein the third potentialis higher than the fourth potential.
 5. The organic light emittingdisplay device according to claim 4, wherein the third potential islower than the first potential.
 6. The organic light emitting displaydevice according to claim 3, wherein during the first period and thesecond period, a low potential driving voltage having a third potentialis applied to the plurality of second power lines.
 7. The organic lightemitting display device according to claim 3, wherein a low potentialdriving voltage having a fourth potential is applied to the plurality ofsecond power lines during each of the first period and the secondperiod.
 8. The organic light emitting display device according to claim2, wherein a high potential driving voltage having a first potential isapplied to the plurality of first power lines during the first periodand the second period, a low potential driving voltage having a thirdpotential is applied to the plurality of second power lines during thefirst period, a low potential driving voltage having a fourth potentialis applied to the plurality of second power lines during the secondperiod, wherein the third potential is higher than the fourth potential.9. The organic light emitting display device according to claim 2,wherein the first gate voltage and the second gate voltage are highpotentials only during one horizontal period of the first period. 10.The organic light emitting display device according to claim 2, whereinthe first gate voltage is a high potential only during one horizontalperiod of the first period and the second gate voltage is a highpotential during the first period in its entirety.
 11. The organic lightemitting display device according to claim 10, wherein the highpotential of the second gate voltage is lower than a sum of the highpotential driving voltage applied during the first period and athreshold voltage of the second switching transistor.
 12. The organiclight emitting display device according to claim 1, wherein the highpotential of the second gate voltage is a sum of the high potentialdriving voltage applied during the first period and a threshold voltageof the second switching transistor.
 13. The organic light emittingdisplay device according to claim 2, wherein a high potential drivingvoltage having a second potential is applied to the plurality of firstpower lines during each of the first period and the second period. 14.An organic light emitting display device, comprising: a plurality ofdata lines; a plurality of power lines extending in a same direction asthe plurality of data lines; a plurality of gate lines intersecting theplurality of data lines and the plurality of power lines; and aplurality of pixels applied with voltages from the plurality of datalines, the plurality of power lines, and the plurality of gate lines,wherein each of the plurality of pixels includes: a driving transistor;a first switching transistor which applies a data voltage to a gateelectrode of the driving transistor; a second switching transistor whichapplies a high potential driving voltage to a source electrode of thedriving transistor; a storage capacitor which maintains a voltageapplied to the gate electrode and the source electrode of the drivingtransistor; and an organic light emitting diode which is applied with acurrent flowing through the source electrode of the driving transistorto emit light, wherein the driving transistor and the second switchingtransistor are connected to a same power line from the plurality ofpower lines, wherein the plurality of gate lines includes a plurality offirst gate lines connected to the first switching transistors and aplurality of second gate lines connected to the second switchingtransistors and a high potential of a second gate voltage which isapplied to the plurality of second gate lines is less than a highpotential of a first gate voltage which is applied to the plurality offirst gate lines.
 15. The organic light emitting display deviceaccording to claim 14, wherein a potential of a voltage applied to thesame power line rises during a period when the organic light emittingdiode emits light.